// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: rstmgr

  // Top level dut name (sv module).
  dut: rstmgr

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")}

  // Testplan hjson file.
  testplan: "{self_dir}/../data/rstmgr_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{self_dir}/../data/rstmgr.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                // Just run the stress_all sequence, and don't inject random
                // resets since we may get overlapping resets due to sequences
                // that inject them.
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
                ]

  // Specific exclusion files.
  vcs_cov_excl_files: ["{self_dir}/cov/rstmgr_unr_excl.el"]

  // Overrides
  overrides: [
    {
      name: design_level
      value: "top"
    }
    {
      name: default_vcs_cov_cfg_file
      value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/rstmgr_cover.cfg+{self_dir}/cov/rstmgr_tgl_excl.cfg"
    }
  ]

  // Add additional tops for simulation.
  sim_tops: ["rstmgr_bind", "rstmgr_cov_bind",
             "sec_cm_prim_sparse_fsm_flop_bind",
	     "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: rstmgr_base_test
  uvm_test_seq: rstmgr_base_vseq

  // Enable cdc instrumentation.
  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: rstmgr_smoke
      uvm_test_seq: rstmgr_smoke_vseq
    }
    {
      name: rstmgr_por_stretcher
      uvm_test_seq: rstmgr_por_stretcher_vseq
    }
    {
      name: rstmgr_reset
      uvm_test_seq: rstmgr_reset_vseq
    }
    {
      name: rstmgr_sw_rst_reset_race
      uvm_test_seq: rstmgr_sw_rst_reset_race_vseq
    }
    {
      name: rstmgr_sw_rst
      uvm_test_seq: rstmgr_sw_rst_vseq
    }
    {
      name: rstmgr_sec_cm_scan_intersig_mubi
      uvm_test_seq: rstmgr_sec_cm_scan_intersig_mubi_vseq
    }
    {
      name: rstmgr_leaf_rst_cnsty
      uvm_test_seq: rstmgr_leaf_rst_cnsty_vseq
    }
    {
      name: rstmgr_leaf_rst_shadow_attack
      uvm_test_seq: rstmgr_leaf_rst_shadow_attack_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["rstmgr_smoke"]
    }
  ]
}
